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| d a t a sh eet product speci?cation supersedes data of 1998 feb 23 2003 jul 10 integrated circuits 74HC74; 74hct74 dual d-type flip-flop with set and reset; positive-edge trigger
2003 jul 10 2 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 features wide supply voltage range from 2.0 to 6.0 v symmetrical output impedance high noise immunity low power dissipation balanced propagation delays esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. general description the 74hc/hct74 is a high-speed si-gate cmos device and is pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct74 are dual positive-edge triggered, d-type flip-flops with individual data (d) inputs, clock (cp) inputs, set ( sd) and reset ( rd) inputs; also complementary q and q outputs. the set and reset are asynchronous active low inputs and operate independently of the clock input. information on the data input is transferred to the q output on the low-to-high transition of the clock pulse. the d inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. quick reference data gnd = 0 v; t amb =25 c; t r =t f =6ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. for 74HC74 the condition is v i = gnd to v cc . for 74hct74 the condition is v i = gnd to v cc - 1.5 v. symbol parameter conditions typical unit hc hct t phl /t plh propagation delay c l = 15 pf; v cc =5v ncp to nq, n q1415ns n sd to nq, n q1518ns n rd to nq, n q1618ns f max maximum clock frequency 76 59 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per ?ip-?op notes 1 and 2 24 29 pf 2003 jul 10 3 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 function tables table 1 see note 1 table 2 see note 1 note 1. h = high voltage level; l = low voltage level; x = dont care; - = low-to-high cp transition; qn+1 = state after the next low-to-high cp transition. ordering information input output sd rd cp d q q lhxxhl hlxxlh llxxhh input output sd rd cp d qn+1 qn+1 hh - llh hh - hhl type number package temperature range pins package material code 74HC74n - 40 to +125 c 14 dip14 plastic sot27-1 74hct74n - 40 to +125 c 14 dip14 plastic sot27-1 74HC74d - 40 to +125 c 14 so14 plastic sot108-1 74hct74d - 40 to +125 c 14 so14 plastic sot108-1 74HC74db - 40 to +125 c 14 ssop14 plastic sot337-1 74hct74db - 40 to +125 c 14 ssop14 plastic sot337-1 74HC74pw - 40 to +125 c 14 tssop14 plastic sot402-1 74hct74pw - 40 to +125 c 14 tssop14 plastic sot402-1 74HC74bq - 40 to +125 c 14 dhvqfn14 plastic sot762-1 74hct74bq - 40 to +125 c 14 dhvqfn14 plastic sot762-1 2003 jul 10 4 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 pinning pin symbol description 11 rd asynchronous reset-direct input (active low) 2 1d data input 3 1cp clock input (low-to-high, edge-triggered) 41 sd asynchronous set-direct input (active low) 5 1q true ?ip-?op output 61 q complement ?ip-?op output 7 gnd ground (0 v) 82 q complement ?ip-?op output 9 2q true ?ip-?op output 10 2 sd asynchronous set-direct input (active low) 11 2cp clock input (low-to-high, edge-triggered) 12 2d data input 13 2 rd asynchronous reset-direct input (active low) 14 v cc positive supply voltage handbook, halfpage mna417 74 1 2 3 4 5 6 7 8 14 13 12 11 10 9 1rd 1d 1cp 1sd 1q 1q gnd 2q 2q 2sd 2cp 2d 2rd v cc fig.1 pin configuration dip14, so14 and (t)ssop14. handbook, halfpage 114 gnd (1) 1rd v cc 7 2 3 4 5 6 1d 1cp 1sd 1q 1q 13 12 11 10 9 2rd 2d 2cp 2sd 2q 8 gnd top view 2q mnb038 fig.2 pin configuration dhvqfn14. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. 2003 jul 10 5 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 mna418 handbook, halfpage rd ff sd 410 q 1q 2q 1q 2q 5 9 2 12 3 11 6 8 q 1sd cp 2cp 1cp 2d 1d d 2sd 113 1rd 2rd fig.3 logic symbol. handbook, halfpage mna419 6 3 2 c1 4 s 1d 1 r 5 8 11 12 c1 10 s 1d 13 r 9 fig.4 iec logic symbol. handbook, halfpage rd ff sd 4 q 1q 1q 5 2 3 6 q 1sd cp 1cp 1d d 1 1rd mna420 rd ff sd 10 q 2q 2q 9 12 11 8 q 2sd cp 2cp 2d d 13 2rd fig.5 functional diagram. 2003 jul 10 6 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 handbook, full pagewidth mna421 sd cp rd d c c q c c c c c c q c c fig.6 logic diagram (one flip-flop). 2003 jul 10 7 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so14 packages: above 70 c derate linearly with 8 mw/k. for ssop14 and tssop14 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 c derate linearly with 4.5 mw/k. for dip14 packages: above 70 c derate linearly with 12 mw/k. symbol parameter conditions 74HC74 74hct74 unit min. typ. max. min. typ. max. v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0 - v cc v v o output voltage 0 - v cc 0 - v cc v t amb operating ambient temperature - 40 +25 +125 - 40 +25 +125 c t r ,t f input rise and fall times v cc = 2.0 v -- 1000 -- 500 ns v cc = 4.5 v - 6.0 500 - 6.0 500 ns v cc = 6.0 v -- 400 -- 500 ns symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v or v i >v cc + 0.5 v; note 1 - 20 ma i ok output diode current v o < - 0.5 v or v o >v cc + 0.5 v; note 1 - 20 ma i o output source or sink current - 0.5v 2003 jul 10 9 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 family 74hct at recommended operating conditions; voltages are referenced to gnd (groun d=0v). note 1. all typical values are measured at t amb =25 c. remark to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given here. to determine d i cc per input, multiply this value by the unit load coef?cient shown in the table. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c; note 1 v ih high-level input voltage 4.5 to 5.5 2.0 1.6 - v v il low-level input voltage 4.5 to 5.5 - 1.2 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 4.0 ma 4.5 3.84 4.32 - v v ol low-level output voltage v i =v ih or v il ; i o = 4.0 ma 4.5 0.33 0.15 - v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 40 m a d i cc additional quiescent supply current per input v i =v cc - 2.1 v other inputs at v cc or gnd; i o =0 4.5 to 5.5 - 100 450 m a t amb = - 40 to +125 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il ; i o = - 4.0 ma 4.5 3.7 -- v v ol low-level output voltage v i =v ih or v il ; i o = 4.0 ma 4.5 -- 0.4 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i cc quiescent supply current v i =v cc or gnd; i o =0 5.5 -- 80 m a d i cc additional quiescent supply current per input v i =v cc - 2.1 v other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 490 m a input unit load coefficient nd 0.70 n rd 0.70 n sd 0.80 ncp 0.80 2003 jul 10 10 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 ac characteristics family 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c t phl /t plh propagation delay ncp to nq, n q see fig.7 2.0 - 47 220 ns 4.5 - 17 44 ns 6.0 - 14 37 ns propagation delay n sd to nq, n q see fig.8 2.0 - 50 250 ns 4.5 - 18 50 ns 6.0 - 14 43 ns propagation delay n rd to nq, n q see fig.8 2.0 - 52 250 ns 4.5 - 19 50 ns 6.0 - 15 43 ns t thl /t tlh output transition time see fig.7 2.0 - 19 95 ns 4.5 - 719ns 6.0 - 616ns t w clock pulse width high or low see fig.7 2.0 100 19 - ns 4.5 20 7 - ns 6.0 17 6 - ns set or reset pulse width low see fig.8 2.0 100 19 - ns 4.5 20 7 - ns 6.0 17 6 - ns t rem removal time set or reset see fig.8 2.0 40 3 - ns 4.5 8 1 - ns 6.0 7 1 - ns t su set-up time nd to ncp see fig.7 2.0 75 6 - ns 4.5 15 2 - ns 6.0 13 2 - ns t h hold time ncp to nd see fig.7 2.0 3 - 6 - ns 4.5 3 - 2 - ns 6.0 3 - 2 - ns f max maximum clock pulse frequency see fig.7 2.0 4.8 23 - mhz 4.5 24 69 - mhz 6.0 28 82 - mhz 2003 jul 10 11 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 t amb = - 40 to +125 c t phl /t plh propagation delay ncp to nq, n q see fig.7 2.0 -- 265 ns 4.5 -- 53 ns 6.0 -- 45 ns propagation delay n sd to nq, n q see fig.8 2.0 -- 300 ns 4.5 -- 60 ns 6.0 -- 51 ns propagation delay n rd to nq, n q see fig.8 2.0 -- 300 ns 4.5 -- 60 ns 6.0 -- 51 ns t thl /t tlh output transition time see fig.7 2.0 -- 110 ns 4.5 -- 22 ns 6.0 -- 19 ns t w clock pulse width high or low see fig.7 2.0 120 -- ns 4.5 24 -- ns 6.0 20 -- ns t w set or reset pulse width low see fig.8 2.0 120 -- ns 4.5 24 -- ns 6.0 20 -- ns t rem removal time set or reset see fig.8 2.0 45 -- ns 4.5 9 -- ns 6.0 8 -- ns t su set-up time nd to ncp see fig.7 2.0 90 -- ns 4.5 18 -- ns 6.0 15 -- ns t h hold time ncp to nd see fig.7 2.0 3 -- ns 4.5 3 -- ns 6.0 3 -- ns f max maximum clock pulse frequency see fig.7 2.0 4.0 -- mhz 4.5 20 -- mhz 6.0 24 -- mhz symbol parameter test conditions min. typ. max. unit waveforms v cc (v) 2003 jul 10 12 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 family 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf. symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c t phl /t plh propagation delay ncp to nq, n q see fig.7 4.5 - 18 44 ns propagation delay n sd to nq, n q see fig.8 4.5 - 23 50 ns propagation delay n rd to nq, n q see fig.8 4.5 - 24 50 ns t thl /t tlh output transition time see fig.7 4.5 - 719ns t w clock pulse width high or low see fig.7 4.5 23 9 - ns set or reset pulse width low see fig.8 4.5 20 9 - ns t rem removal time set or reset see fig.8 4.5 8 1 - ns t su set-up time nd to ncp see fig.7 4.5 15 5 - ns t h hold time ncp to nd see fig.7 4.5 +3 - 3 - ns f max maximum clock pulse frequency see fig.7 4.5 22 54 - mhz t amb = - 40 to +125 c t phl /t plh propagation delay ncp to nq, n q see fig.7 4.5 -- 53 ns propagation delay n sd to nq, n q see fig.8 4.5 -- 60 ns propagation delay n rd to nq, n q see fig.8 4.5 -- 60 ns t thl /t tlh output transition time see fig.7 4.5 -- 22 ns t w clock pulse width high or low see fig.7 4.5 27 -- ns set or reset pulse width low see fig.8 4.5 24 -- ns t rem removal time set or reset see fig.8 4.5 9 -- ns t su set-up time nd to ncp see fig.7 4.5 18 -- ns t h hold time ncp to nd see fig.7 4.5 3 -- ns f max maximum clock pulse frequency see fig.7 4.5 18 -- mhz 2003 jul 10 13 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 ac waveforms handbook, full pagewidth mna422 t h t su t h t phl t phl t w t plh t plh t su 1/f max v m v m v m v m v i gnd v i gnd ncp input nd input v oh v ol nq output v oh v ol nq output fig.7 the clock (ncp) to output (nq, n q) propagation delays, the clock pulse width, the nd to ncp set-up, the ncp to nd hold times, the output transition times and the maximum clock pulse frequency. the shaded areas indicate when the input is permitted to change for predictable output performance. 74HC74: v m = 50%; v i = gnd to v cc . 74hct74: v m = 1.3 v; v i = gnd to 3 v. 2003 jul 10 14 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 handbook, full pagewidth mna423 t rem t phl t phl t w t plh t plh v m v m v m t w v m v m v i gnd v i gnd nsd input v i gnd nrd input ncp input v oh v ol nq output v oh v ol nq output fig.8 the set (n sd) and reset (n rd) input to output (nq, n q) propagation delays, the set and reset pulse widths and the n rd, n rd to ncp removal time. 74HC74: v m = 50%; v i = gnd to v cc . 74hct74: v m = 1.3 v; v i = gnd to 3 v. 2003 jul 10 15 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 handbook, full pagewidth open gnd v cc v cc v i v o mna183 d.u.t. c l r t r l = 1 k w pulse generator s1 fig.9 load circuitry for switching times. definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. test s1 t pzh gnd t pzl v cc t phz gnd t plz v cc 2003 jul 10 16 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 package outlines unit a max. 1 2 (1) (1) b 1 cd (1) z ee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot27-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.2 4.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.087 0.17 0.02 0.13 050g04 mo-001 sc-501-14 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 14 1 8 7 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. dip14: plastic dual in-line package; 14 leads (300 mil) sot27-1 2003 jul 10 17 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1 2003 jul 10 18 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2 2003 jul 10 19 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index 2003 jul 10 20 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 2003 jul 10 21 philips semiconductors product speci?cation dual d-type ?ip-?op with set and reset; positive-edge trigger 74HC74; 74hct74 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/03/pp 22 date of release: 2003 jul 10 document order number: 9397 750 11259 |
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